(1) Field of the Invention
The present invention relates to ultra large scale integrated (ULSI) circuits on semiconductor substrates, and more particularly relates to a method for forming reliable borderless contacts in the interlevel dielectric (ILD) layer over the active device area/shallow trench isolation interface.
(2) Description of the Prior Art
To continue increasing the circuit density on future Ultra Large Scale Integration (ULSI) circuits, downscaling is required on the semiconductor chips. This downscaling becomes increasingly difficult as the photolithography resolution improves and minimum feature sizes are reduced in the next generation of devices to deep submicrometer dimensions (e.g., 0.25 and 0.18 um). One method of increasing circuit density is to replace the conventional LOCOS (LOCal Oxidation of Silicon) isolation with a Shallow Trench Isolation (STI) that surrounds and electrically isolates the individual device areas on the silicon substrate. Briefly, the STI is formed by anisotropically etching trenches (with little etch bias) and filling the trenches with a chemical-vapor-deposited (CVD) oxide that is then etched back or chemically/mechanically polished (CMP) back to form a planar surface with the substrate. This replaces the LOCOS isolation which is formed by a thermal oxidation, which by its very nature, oxidizes laterally and intrudes on the device area. Another problem that limits the downscaling is the difficulty in making reliable borderless contacts to the device areas that overlap the STI to reduce the design rules (layout). When making the contact openings for the borderless contacts in an overlying ILD layer, overetching of the STI can result in exposing the shallow diffused junction in the substrate at the sidewall of the upper portion of the trench. The borderless contacts formed by a metal plug in the contact openings short the diffused junction to the substrate body destroying the intended circuit function. This borderless contact problem is best depicted in FIG. 1, in which a trench 2 containing an STI 12 is formed in a Pxe2x88x92 doped silicon substrate 10, and an N+ shallow diffused contact 19(N+) is formed in the substrate top surface. When an ILD layer 22 is deposited and a borderless contact opening 4 is etched, the STI 12 is overetched. A metal contact 24 formed in the opening 4 results in N+ contact 19 shorting to the substrate 10 across the P/N junction at point A in the trench sidewall.
Several methods of overcoming these problems are depicted in the prior art drawings in FIGS. 2 through 5. FIG. 2 shows a portion of an FET gate electrode 16 with a gate oxide 14 and two STI regions 12. The STI 12 is formed having portion 12xe2x80x2 extending above the surface of the substrate 10. Silicon nitride sidewall spacers 13 are then formed on the sidewalls of portions 12xe2x80x2 by depositing and etching back a Si3N4 layer. Unfortunately, when the Si3N4 spacers 13 encroach onto the device-areas, as depicted for the STI 12 on the left, the design rules must be relaxed to provide the necessary area for the device, and therefore limits the device packing density. As shown for the STI 12 on the right, if the Si3N4 spacers do not extend over the interface at A, the STI can be overetched when the borderless contact openings are etched, causing electrical shorts between the shallow N+ doped contacts 19 and the Pxe2x88x92 substrate. FIG. 3 shows another approach in which the STI 12 is recessed using a wet-etch dip, and a silicon nitride sidewall spacer 13 is formed by depositing and anisotropically etching back. After recessing the STI 12 and before forming the silicon nitride sidewall spacers 13, a polysilicon layer 16 is deposited and patterned to form gate electrodes 16 and concurrently to form polysilicon protective visors 15. However, these closely spaced polysilicon visors 15 can result in poor field isolation across the narrow STI 12 between adjacent device areas.
FIG. 4 shows a method in which the STI 12 is recessed and the Si3N4 visors 13xe2x80x2 are formed when the Si3N4 layer is anisotropically etched back to form the sidewall spacers 13 on the gate electrode 16. However, in this method the gate oxide at point B under the gate electrode is eroded when the STI 12 is recessed by etching, and undercutting of the STI 12 at regions C during etching can result in peeling of the patterned polysilicon layer 16xe2x80x2 and can result in thinning of the STI region. A similar method as depicted in FIG. 4 is described in the paper entitled xe2x80x9cA 2.9 um2 Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 um High Performance CMOS Logicxe2x80x9d by K. Noda et al. in IEDM 97 of IEEE, pp. 847-850. Finally, a fourth method is shown in FIG. 5. In this approach a blanket Si3N4 layer is used to protect the interface A when the borderless contact openings are etched. However, the high stress due to the Si3N4 layer can cause dislocation in the substrate and high leakage currents at the N+/Pxe2x88x92 junction between the N+ contact 19 and the Pxe2x88x92 doped silicon substrate.
U.S. Pat. No. 4,981,813 to Bryant et al. describes a method for forming the conventional LOCOS with reduced bird""s beak penetration into the active device area using silicon nitride spacers, thereby allowing increased circuit density. U.S. Pat. No. 5,173,444 to Kawamura describes a method similar to Bryant et al., also using silicon nitride sidewall spacers to reduce the bird""s beak and increase circuit density. U.S. Pat. No. 5,652,176 to Maniar et al. uses a liner composed of aluminum nitride in the STI trench prior to filling the trench with SiO2. When borderless contacts are etched over the source/drain area-STI interface, the aluminum nitride is retained on the sidewall of the trench and prevents shorting between the source/drain contact and Pxe2x88x92 substrate. Fazan et al. in U.S. Pat. No. 5,433,794 teach a method for making a sidewall spacer, composed of an insulating layer such as SiO2 or Si3N4, on the sidewall of a raised STI. The insulating spacers overlap the active device regions and are used to reduce high electric fields (corner effect problem) that would cause device leakage currents. Cronin et al. in U.S. Pat. No. 4,944,682 teach a method for forming borderless contacts (self-aligned contacts) to polysilicon gate electrodes, but do not address borderless contacts to STI. U.S. Pat. No. 5,651,857 to Cronin et al. also teaches a method that form borderless contacts (self-aligned contacts) to polysilicon FET gate electrodes, but does not address making borderless contacts over source/drain areas-STI interfaces.
There is still a strong need in the semiconductor industry to provide improved borderless contacts to shallow diffused contact areas, such as FET source/drain areas on substrates, that also overlap STI without causing shorts between the shallow diffused contacts and the substrate.
It is a principal object of the present invention to provide borderless contacts to improve circuit density.
It is another object of this invention to provide a method for making more reliable borderless contacts that extend over the active device area/shallow trench isolation interface on a silicon substrate.
Still another object of this invention is to provide a silicon nitride visor (protective covering) on the edge of the active device region to prevent electrical shorting between the substrate and the diffused junction when borderless contacts are made.
A further object of this invention is to prevent erosion of the gate oxide when the shallow trench isolation is recessed for forming the visor.
In summary, these objectives are achieved by this invention, which forms reliable borderless contact openings to the silicon substrate that extend over the active device area/shallow trench isolation (STI) interface. More specifically, the method of a first embodiment utilizes a second silicon nitride (Si3N4) layer to form visors or protective coverings over the edge of the silicon active device areas to prevent electrical shorting of the diffused surface junctions to the substrate when borderless contacts are formed.
The invention begins by providing a semiconductor substrate. The most commonly used substrate in the semiconductor industry is composed of single crystal silicon. Active device areas are provided by etching trenches in the substrate and filling the trenches with a silicon oxide (SiO2). The oxide is made planar with the substrate surface by various means. A gate oxide is grown on the active device areas, and a polysilicon layer (or a polycide layer) is deposited over the substrate and patterned to form FET gate electrodes over the active device areas. Lightly doped source/drain areas are formed by ion implantation to improve device performance of deep sub-micron devices. A conformal first Si3N4 layer is deposited and etched back to form sidewall spacers on the gate electrodes, and a second ion implantation is used to form source/drain contact areas.
During the formation of the STI and the patterning of the polysilicon layer, the interface between the active device areas and the STI can be electrically degraded, making it difficult to etch reliable borderless contacts in an insulating layer to the substrate. To achieve reliable interfaces while providing good borderless contacts, the invention consists of recessing the shallow trench isolation and exposing the upper portion of the sidewalls of the active device areas at the source/drain implanted junction while the Si3N4 sidewall spacers prevent the etching from attacking the gate oxide under the gate electrodes. The STI can be recessed using a controlled dip etch in hydrofluoric (HF) acid solution. A silicon oxide stress-release layer is formed over the edge of the active device areas on the substrate, for example by thermal oxidation. A conformal second Si3N4 layer is deposited and anisotropically etched back to form a visor to prevent the shallow source/drain implanted junctions from shorting to the substrate when the borderless contacts extend over the interface. It is now possible to deposit an interlevel dielectric (ILD) layer on the substrate and to etch in the ILD layer borderless contact openings to the active device areas that extend over the STI without causing source/drain-to-substrate shorting when metal plugs are formed in the contact openings.
By the method of a second embodiment, the Si3N4 spacers formed from the first Si3N4 layer are replaced with disposable SiO2 spacers. A conformal SiO2 layer is deposited and is etched back to form the spacers. The disposable spacers are removed at the same time that the STI is recessed using the HF dip etch. The remaining process steps are the same as in the first embodiment except that when the second Si3N4 layer is etched back to form the visor, the sidewall spacers on the gate electrodes are also formed. In the second embodiment, the source/drain implants can be implemented first before the removal of the disposable SiO2 spacers, and the lightly doped drain (LDD) implant can be performed after the removal of the disposable SiO2 sidewall spacers and prior to forming the visor and Si3N4 sidewall spacers.